The invention relates to integrated circuit (IC) construction for planar, monolithic, PN-junction-isolated devices. In the conventional structures vertically arrayed NPN transistors can be fabricated to have high Beta (on the order of several hundred) and high operating frequencies (on the order of several hundred MHz). Vertical PNP transistors are commonly substrate dedicated (or connected) collector devices that have a relatively low frequency response, on the order of several tens of MHz. Where a completely isolated PNP device is required, the lateral transistor is ordinarily employed. These devices often display low Beta values less than about 100 and have poor frequency response on the order of several MHz. When lateral PNP transistors are combined with NPN transistors in integrated circuits, unexpected instabilities and other peculiarities can develop to plague the circuit designer who must resort to circuit compromises.
Many attempts have been made to provide high performance PNP transistors for IC use in a process that is compatible with the basic planar NPN structures so that high performance circuits can be achieved. However, these attempts have not been completely successful. Typically, a complementary transistor process does not permit the individual optimization of both of the complementary transistors. The performance of one of the complementary devices often suffers when the process is adjusted to optimize the other device. For example, if the process is altered to improve the PNP transistors, the NPN transistors are degraded.
One example of a successful complementary device process is found in the James L. Dunkley U.S. Pat. No. 3,901,735 which issued to the assignee of the present invention. Here complementary devices are produced in an epitaxial layer that is isolated by diffusion into tubs that contain the active devices. A combination of up-diffusion along with the conventional top surface diffusion is employed to produce isolation diffusion walls which act to isolate sections of the deposited epitaxial layer. Since the isolation diffusion acts to penetrate the epitaxial layer from both top and bottom, the diffusion must extend approximately half way through the layer. This not only reduces the time of isolation diffusion, it also reduces the extent of lateral isolation diffusion and thereby makes for more efficient utilization of the IC surface area.
Another aspect of IC design is related to the thickness of the epitaxial layer. It is desirable to make this layer as thin as possible without degrading device performance. The use of aluminum diffusion in reducing the epitaxial layer thickness is set forth in Amolak R. Ramde et al. U.S. Pat. No. 4,512,816 which also issued to the assignee of the present invention. Here aluminum is employed as the isolation diffusion species. Since Aluminum diffuses much more rapidly than Boron, the usual P-type dopant element in silicon, it can be used to create the required isolation in a relatively short time. This reduces buried layer up-diffusion in the conventional IC structure and therefore permits the use of thinner epitaxial layers. This also reduces the lateral surface diffusion of the isolation and results in increased circuit component density.
The teaching in the above two patents is incorporated herein by reference.
It is desirable to have a complementary IC transistor process for making high voltage (above about 40 volts) transistors wherein the complementary transistors can be individually optimized for their operating characteristics.